Optical projection lithography systems are used to make large scale integrated circuits, or chips. A principal advantage of these systems is that they may be used to manufacture extremely fine patterns. Typically, masks or reticles are created that contain the pattern for a layer of material that will be used in the construction of a microchip. Light is projected through such a mask onto a photosensitive layer on a semiconductor wafer; further processing of the photosensitive material results in the pattern on the mask being transferred to the photosensitive film, which is then later used to create corresponding patterns by means such as etching, depositing, oxidizing or implanting materials on the semiconductor wafer.
Distortions and imperfections that exist within the optical projection mask, from the intended pattern, typically result in a lower quality pattern that is transferred to the photosensitive film on the wafer, and that is then transferred into the materials on the semiconductor wafer. The more distortions, the less likely the final resulting microchip circuitry will work properly, if at all.
Consequently, it is important that the mask be properly designed and manufactured. Because chip designs are usually pushing the limits of the small sizes of patterns that can be created on a chip, the process of transferring chip design shapes to a mask typically induces distortions in the'shapes as they appear on the mask. In particular, inner and outer corners are not only not square but have different radii of curvature. So-called resolution enhancements such as serifs commonly used for optical proximity correction may be badly distorted on the mask since they are typically smaller than the nominal minimum feature size for a given mask level. Hence, characterizing these distortions and taking them into account when designing a mask can significantly improve the quality of the mask that is created, thereby also potentially resulting in considerably improved printed patterns on the wafer. Since these effects may be important in determining the ultimate wafer level image, it is necessary to include them in the overall modeling strategy used to predict the printed shapes on a semiconductor wafer, given the design layout data.